High speed testing of integrated circuit bus structures is an emerging technology. The rapid doubling of digital signal speeds, now reaching from 56 Gbps (giga bits per second, where giga is 1,000,000,000) to 112 Gbps in state-of-the-art circuits, requires new measurement solutions. Additionally, it is not sufficient in a test to simply apply a traditional test signal and evaluate a response within the given specifications. By the very nature of tests and the need to detect and diagnose faults and failures, well controlled out of specification signals need to be evaluated. For example, it is preferable not only to measure noise that is on a signal to determine whether it is within tolerable limits, but to also conduct a comprehensive test to generate controlled noise to make a determination whether a unit under test (UUT) is good or faulty.
Moreover, when the bus speeds are greater than 1 Gbps, standard communication protocols are used. These include synchronous optical network (SONET), Gigabit Ethernet (GBE), fiber channel (FC), and Optical Internetworking Forum (OIF). The approaches to input/output in the Gbps range differ primarily based on clock speeds and the architectures used. Global clock I/O architecture, where a single clock is tied to all parts of the system, is common for lower speed applications. When speeds of 200 Mbps are reached, however, a large difference (skew) exists between the clock's arrival times at one module as compared with another. To overcome these limitations, the Source Synchronous (SS) I/O architecture was introduced that essentially sends a strobe signal along with the data stream so that the receiving circuit can use the strobe to clock the signal. This helps to reduce clock skewing error. The SS architecture can deal with signal integrity degradations for up to 1 Gbps.
For bit rates above 1 Gbps, a serializer/deserializer (SerDes) data transfer approach may be employed. In addition to transferring data bits serially from transmitter to receiver, the transmitter embeds the clock into the bit stream. This is accomplished in several ways, with the most common being a 8 b/10 b encoding scheme. Essentially, the method maps 8-bit data into 10-bit data format so that transitions between 1s and 0s in the bit stream will be mostly balanced. This provides sufficient information to be able to decipher the clock rate. On the receiver side a clock recovery circuit, usually a phase locked loop (PLL), is used to fully recover the clock and a dual decoder extracts the clock from the data and reconstructs it to the original 8-bit data.
One of the most important failure modes that have to be characterized in embedded clock architectures is phase jitter. Phase jitter is a time deviation of an edge transition from its ideal time and location, and is caused by various sources of noise. The total jitter breaks down into a deterministic jitter (DJ) and a random jitter (RJ). Each of these in turn can be broken down further, where random jitter includes Gaussian jitter (GJ) and multiple Gaussian jitter (MGI), and deterministic jitter includes data dependent jitter (DDJ), periodic jitter (PJ), and bounded-uncorrelated jitter (BUJ). DDJ breaks down further into duty cycle distortion (DCD) and inter-symbol interference (ISI). One of the great challenges of high speed testing is to separate the various jitter types as they each communicate different information about the true nature of the failure.
Testing embedded clock for signals in excess of 1 Gbps utilizes a combination of tests, including jitter, noise and bit error rate (BER), collectively referred to as JNB tests (for jitter, noise and BER combined). They can be categorized as follows:
1. JNB output test—Verifies the performance of the transmitter or the transmitter plus the medium or channel. It may also include testing the reference clock.
2. JNB tolerance test—Involves setting the worst-case jitter and noise conditions at the receiver input pin and measuring the BER at its output.
3. JNB system test—Checks the overall BER comparing data bits received by the receiver against those sent by the transmitter.
A number of different types of delays can disturb the digital portions of these high speed I/O circuits, for which tests need to be developed. These include, but are not limited to the following:
1. Transient faults, including slow-to-rise, slow to fall delay faults.
2. Inline-delay faults that are due to resistive interconnect bias, which slow down both rising and falling transitions.
3. Gate-delay faults (also called local delay faults) that become more predominant when the longest path for transition is tested.
4. Path-delay faults, which are similar to gate-delay faults, but it may be caused by multiple gate-delays where one alone would not necessarily cause a failure.
A number of other failure modes peculiar to high speed I/O testing also exists. They include, but are not limited to, the following:
1. Lossy Signal—At multiple Gbps data rates a digital waveform appears to be an analog waveform at the receiver input because of the frequency-dependent lossy property of the channel and medium (such as PCB traces, cables, connectors).
2. Unit Interval (UI) shrinkage—UI is the data period, which is the inverse of the frequency at the which data is transmitted. As data rate increases jitter reduces the data valid window—generally termed as available portion of UI, the period during which digital bit can exist. The effectively useable UI becomes shorter and shorter as frequency increases.
3. Equalization failure—Equalization compensates for frequency-dependent losses (rolling off at the high end) characteristics of the channel or media, and the clock recovery circuit helps to track the data even though it is jittery. A highly jittery transmitter may work well with a particular receiver that has good equalization, while it fails with defective equalization. Such a transmitter may be misdiagnosed as faulty when it is not. This may make it difficult to diagnose the faulty components or could cause false alarms.
4. Crosstalk—Maximum Aggressor (MA) is a fault model that defines faults based on the resulting crosstalk error. Effects include positive glitch, negative glitch, rising delay and falling delay. For a set of N interconnects, the MA fault model considers the collective aggressor effects on a given victim line Yi with all other N−1 wires act as aggressors.
Current high speed, state-of-the-art automated test equipment (ATE) are primarily aimed at testing integrated circuits (ICs) and system-on-chip (SOC) applications. The ATE takes advantage of design for testability (DFT) techniques, including built-in self-test (BIST) affecting the device under test (DUT) prior to design finalization. Boards and modules, such as shop replaceable units (SRUs) and line replaceable units (LRUs) are typically not designed with sufficient DFT to allow the same test methods to be utilized. While efforts towards better DFT of LRUs and SRUs are encouraged, it would be naïve to expect that all UUTs being tested by commercial and military board and system ATEs will have the desired DFT features to assist tests sufficiently to overcome all of the obstacles that the actual system encounters. The need persists and is steadily increasing for test tools that not only handle conventional data buses, but also the testing needs of new high speed data buses that are being incorporated in the latest system enhancements. Next-generation UUTs are designed with high-throughput buses ranging from 100 Mbps to 1500 Mbps, and utilize various data buses (e.g., Firewire, RS-422, Wi-Fi, HDMI, and SATA). It is very likely that soon Universal Serial Bus (“USB”) 3.0 buses will be ubiquitous in the majority of systems, and these buses can operate in the 5 Gbps range. USB 3.1 is already commercially available, and it transfers data at 10 Gbps. All this drives a need for faster digital communication buses in automatic test equipment to facilitate testing, file upload and download, and other UUT interactions.
Traditionally, an automatic test equipment (ATE), sometimes called automatic test system (ATS), has been used to apply stimuli to and collect responses from a unit under test (UUT). This is normally accomplished by switching stimulus and measurement instruments in the ATE to UUT input and output pins, respectively. The stimulus and measurement instruments can be custom designed and built within the ATE, or more likely commercial off the shelf (COTS) general purpose instruments that are patched together with switching circuits. The issues with either built-in instrumentations or COTS instruments are that they are built with today's components but need to be able to test for tomorrow's circuits. Thus they either drop behind the performance curve fast or have to procure very expensive components (e.g., SiGe, or GaAs) to build these measurement instruments and inflate the cost. Since these COTS instruments need to address a generic (wider) application, they usually have much more capabilities that are not needed for ATE purposes, thus further inflating their price. For custom built-in instruments, their applications are dedicated within an ATE system, thus the large R & D required to develop them are amortized over a limited number of ATE systems, also inflating the cost.
A test program set (TPS) is developed for each UUT by a test engineer through an often long, tedious and challenging process at a high cost over a considerable duration of time. The TPS consists of three elements, namely, a test program in a language the ATE understands, documentation about the theory behind each test for debug and diagnostic purposes, and an interface test adaptor (ITA) (sometimes called interface device or ID) that mates the ATE and the UUT both mechanically and electronically so that the ATE can test the UUT. A major challenge faced by the industry is that the ATE is not able to address current technology capabilities of the UUT. As unit under test (UUT) technology capabilities improve in various parameters, such as in higher speed operations, ATEs become less proficient in detecting their faults. It is unfeasible to continuously replace ATEs with newer and updated models each time UUT technology changes. Unfortunately, over time the gap between existing ATE capabilities and UUT limits becomes more significant, and with constraints in ATE expenditures and configuration changes it is difficult or impossible to effectively test high speed UUTs with existing ATEs. Upgrading ATE capabilities to meet today's high speed applications, if at all possible or feasible, is at best a temporary solution since new, higher speed bus structures are introduced all the time. A related problem is the increased complexity of the tests themselves, requiring ever more complex test equipment and more complicated and time consuming TPS development manually by test engineers. A ubiquitous solution is needed that will allow legacy and existing ATEs to adapt to and test continuously updated and improved high speed UUTs, and to do so within a feasible time and cost constraint.
Moreover, traditional test methods where stimuli are applied and responses collected by the ATE are not properly supported at these high speeds, especially not in current automatic test system environments. New methods and tools are needed that will aid in the support of state-of-the-art bus technologies, and also ensure the integrity, quality, and reliability of the signals and data communication associated with the buses. While it is unfeasible to change either the UUT or the ATE for a required test, the TPS with all its elements can be customized to overcome incompatibilities. Reusable elements within the TPS is a novel concept that has not been utilized. In the present invention, reusable test programs and reusable interfaces are used not only to provide solutions for automatic testing of high speed and complex circuits, but in the process lower the TPS development costs throughout the industry.
Many of these high speed signaling protocols are asynchronous in nature, i.e., the sending and receiving end will test to see if a specified sequence is received at the other end, and failing to receive that, the sending/receiving pair will either change the signaling rate (performance) and/or change the adaptation circuits to try and recover the signals. Each signaling standard, such as USB, SATA, or Ethernet, have their unique protocols. Sometimes, from one version of the standard to another, the protocol can change significantly (e.g., USB 2.0 to USB 3.0). This handshake of the signaling breaks the pattern matching nature of today's ATE architecture, where a single mismatch fails the UUT and sends it to the scrap bin.
The present invention circumvents most, if not all such obsolescence factors by utilizing reconfigurable instruments embedded in a FPGA. If even the current FPGA-based instrument is unable to keep up with UUT characteristic improvements, replacing the FPGA with a more modern and higher performance FPGA can readily “update” the ATE to overcome the obsolescence. As an additional benefit not available in today's ATE, the present invention presents reconfigurable test instruments that facilitate test program set (TPS) reuse. Since TPS development is a costly and time consuming endeavor, a great deal of savings can be gained from reusing TPSs in part or in their entirety in testing other UUTs.